ASIC Design Verification Engineer || Verilog, UVM, Testbench | Simulation || Exp 7+ years
CiscoEntry / JuniorFull-time
- Posted
- 19 Oct 2026
- Location
- Bangalore, India
- Role
- Hardware / Embedded
- Experience
- 1+ years
- Degree
- Bachelor's
- Skills
- Verilog
- Salary
- Not listed in the job ad
The full description is on Cisco's site.