ASIC Engineering Technical Leader (RTL Design/SOC | 8- 14 Years)
CiscoSeniorFull-time
- Posted
- 13 Oct 2026
- Location
- Bangalore, India
- Role
- Hardware / Embedded
- Experience
- 9+ years
- Degree
- Bachelor's
- Skills
- PythonC++Verilog
- Salary
- Not listed in the job ad
The full description is on Cisco's site.