ASIC Design Verification Engineer, Technical Leader
CiscoSeniorFull-time
- Posted
- 1 Oct 2026
- Location
- San Jose, California, US
- Role
- Hardware / Embedded
- Experience
- 8+ years
- Degree
- Bachelor's
- Skills
- PythonVerilog
- Salary
- $186,900 – $267,700 / year, before tax
The full description is on Cisco's site.