ASIC Design Verification Eng II Full Time - United States
CiscoMidFull-time
- Posted
- 18 Sept 2026
- Location
- San Jose, California, US · RTP, North Carolina, US
- Role
- Hardware / Embedded
- Experience
- 0+ years
- Degree
- Bachelor's
- Skills
- PythonVerilog
- Salary
- $125,700 – $203,100 / year, before tax
The full description is on Cisco's site.