ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)
CiscoSeniorFull-time
- Posted
- 22 May 2026
- Location
- Pune, India
- Role
- Hardware / Embedded
- Experience
- 8+ years
- Degree
- Bachelor's
- Skills
- PythonMachine LearningVerilogFPGA
- Salary
- Not listed in the job ad
The full description is on Cisco's site.