CPU RTL Design Engineer
IntelEntry / JuniorFull-time
- Posted
- 15 Oct 2026
- Location
- US, Arizona, Phoenix · US, Texas, Austin
- Role
- Other engineering
- Experience
- 1+ years
- Degree
- Bachelor's
- Skills
- Verilog
- Salary
- $105,650 – $200,340 / year, before tax
The full description is on Intel's site.