Senior ASIC Design Verification Engineer
CiscoSeniorFull-time
- Posted
- 21 Oct 2026
- Location
- San Jose, California, US
- Role
- Hardware / Embedded
- Experience
- 4+ years
- Degree
- Bachelor's
- Skills
- PythonVerilog
- Salary
- $167,700 – $245,200 / year, before tax
The full description is on Cisco's site.