STAGE - FPGA/ASIC – Partitionnement d’un modem en chiplets (F/H)
ThalesIntern / TraineeFull-time
- Posted
- 6 Oct 2026
- Location
- Gennevilliers, Hauts-de-Seine, 92230
- Role
- Hardware / Embedded
- Skills
- VerilogVHDLFPGA
- Salary
- Not listed in the job ad
The full description is on Thales's site.