ASIC Design Verification Engineer, Staff - Principal
SynopsysStaff / Principal
- Posted
- 15 Oct 2026
- Location
- Hsinchu, Taiwan
- Role
- Hardware / Embedded
- Experience
- 15+ years
- Degree
- Bachelor's
- Skills
- PythonC++VerilogEmbedded
- Salary
- Not listed in the job ad
The full description is on Synopsys's site.