R&D Engineering, Staff Engineer - Design Verification/ VIP Verification Engineers
SynopsysStaff / Principal
- Posted
- 17 Sept 2026
- Location
- Delhi, India
- Role
- Hardware / Embedded
- Experience
- 5+ years
- Degree
- Bachelor's
- Skills
- Verilog
- Salary
- Not listed in the job ad
The full description is on Synopsys's site.