Principal Engineer - ASIC Digital Design (Memory Interface IP- HBM/DDR/LPDDR)
SynopsysStaff / Principal
- Posted
- 14 Sept 2026
- Location
- Hyderabad, India
- Role
- Hardware / Embedded
- Experience
- 8+ years
- Skills
- Verilog
- Salary
- Not listed in the job ad
The full description is on Synopsys's site.