Principal RTL Design Engineer, Interconnect IP (PCIe digital design and architecture)
SynopsysStaff / Principal
- Posted
- 15 Apr 2026
- Location
- Bengaluru, India
- Role
- Other engineering
- Experience
- 10+ years
- Degree
- Bachelor's
- Skills
- Python
- Salary
- Not listed in the job ad
The full description is on Synopsys's site.