Senior ASIC Design Engineer – Clocks IP
NVIDIASeniorFull-time
- Posted
- 6 Oct 2026
- Location
- US, CA, Santa Clara · US, TX, Austin
- Role
- Hardware / Embedded
- Experience
- 3+ years
- Degree
- Bachelor's
- Skills
- PythonVerilog
- Salary
- $136,000 – $218,500 / year, before tax
The full description is on NVIDIA's site.