
Senior ASIC Physical Design Engineer, Cache Coherent Interconnects
NVIDIASeniorFull-time
- Posted
- 10 Aug 2026
- Location
- US, CA, Santa Clara · US, OR, Hillsboro
- Role
- Hardware / Embedded
- Experience
- 5+ years
- Skills
- Verilog
- Salary
- $136,000 – $218,500 / year, before tax
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