Senior CPU RTL Design Engineer
IntelSeniorFull-time
- Posted
- 22 Oct 2026
- Location
- US, Texas, Austin · US, Arizona, Phoenix
- Role
- Other engineering
- Experience
- 3+ years
- Degree
- Bachelor's
- Skills
- PythonVerilog
- Salary
- $141,910 – $269,100 / year, before tax
The full description is on Intel's site.