ASIC Design Verification Engineer I (Full Time) - United States
CiscoFull-time
- Posted
- 26 Oct 2026
- Location
- San Jose, California, US · RTP, North Carolina, US · Carlsbad, California, US
- Role
- Hardware / Embedded
- Degree
- Bachelor's
- Skills
- PythonVerilog
- Salary
- $107,800 – $157,400 / year, before tax
The full description is on Cisco's site.